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Results: 53



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41CMOSAIC  RTD 2009 Intra chip stack fluidic cooling: the CMOSAIC demonstrator

CMOSAIC RTD 2009 Intra chip stack fluidic cooling: the CMOSAIC demonstrator

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Source URL: www.nano-tera.ch

Language: English - Date: 2013-05-29 05:14:58
42White Paper  Test Automation of 3D Integrated Systems January 2012

White Paper Test Automation of 3D Integrated Systems January 2012

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Source URL: www.synopsys.com

Language: English - Date: 2014-11-07 12:41:47
43Project ESiP ENIAC Joint Undertaking White Atrium Bldg., Avenue de la Toison d’Or 56-60, 1060 Brussels, Belgium Mail: TO[removed]Brussels, Tel: +[removed], Fax: +[removed]Email: [removed]

Project ESiP ENIAC Joint Undertaking White Atrium Bldg., Avenue de la Toison d’Or 56-60, 1060 Brussels, Belgium Mail: TO[removed]Brussels, Tel: +[removed], Fax: +[removed]Email: [removed]

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Source URL: www.eniac.eu

Language: English - Date: 2013-11-28 09:49:31
44SPTS Catrene 3D presentation_Jan[removed]Compatibility Mode]

SPTS Catrene 3D presentation_Jan[removed]Compatibility Mode]

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Source URL: www.catrene.org

Language: English - Date: 2014-02-03 04:38:44
45

PDF Document

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Source URL: msu.euramet.org

Language: English - Date: 2014-06-13 12:55:32
46j431  Index a acoustic microscopy 406, 407 – bonded wafer thickness, measuring 417

j431 Index a acoustic microscopy 406, 407 – bonded wafer thickness, measuring 417

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Source URL: www.wiley-vch.de

Language: English - Date: 2014-03-31 21:03:45
47Author manuscript, published in

Author manuscript, published in "IP-Embedded System Conference and Exhibition (IP-SoC 2011), Grenoble : France (2011)" IP-SOC 2011 3D Architecture Implementation: A Survey M. H. Jabbar, D. Houzet

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Source URL: hal.archives-ouvertes.fr

Language: English - Date: 2013-09-09 05:31:32
48Microsoft Word - Document1

Microsoft Word - Document1

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Source URL: www.imapsne.org

Language: English - Date: 2014-06-04 09:00:45
49Ziptronix and Customer Pursue Lower-Cost 3D Memory With DBI® Wafer Bonding and Interconnect Technology Ability to Replace Die Stacking with High-strength Wafer Stacking Simplifies Process Flows, Increases Interconnect D

Ziptronix and Customer Pursue Lower-Cost 3D Memory With DBI® Wafer Bonding and Interconnect Technology Ability to Replace Die Stacking with High-strength Wafer Stacking Simplifies Process Flows, Increases Interconnect D

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Source URL: www.ziptronix.com

Language: English - Date: 2012-12-12 11:53:15
50HPCwire: Stacking Stairs Against the Memory Wall

HPCwire: Stacking Stairs Against the Memory Wall

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Source URL: hybridmemorycube.org

Language: English - Date: 2013-05-10 12:23:46